philips semiconductors product specification trenchmos ? transistor phb11N06LT, phd11N06LT logic level fet features symbol quick reference data ? 'trench' technology v dss = 55 v ? very low on-state resistance ? fast switching i d = 11 a ? stable off-state characteristics ? high thermal cycling performance r ds(on) 150 m w (v gs = 5 v) ? low thermal resistance r ds(on) 130 m w (v gs = 10 v) general description n-channel enhancement mode, logic level, field-effect power transistor in a plastic envelope using ' trench ' technology. the device has very low on-state resistance. it is intended for use in dc to dc converters and general purpose switching applications. the phb11N06LT is supplied in the sot404 surface mounting package. the phd11N06LT is supplied in the sot428 surface mounting package. pinning sot428 sot404 pin description 1 gate 2 drain 1 3 source tab drain limiting values limiting values in accordance with the absolute maximum system (iec 134) symbol parameter conditions min. max. unit v dss drain-source voltage t j = 25 ?c to 175?c - 55 v v dgr drain-gate voltage t j = 25 ?c to 175?c; r gs = 20 k w -55v v gs gate-source voltage - 13 v i d continuous drain current t mb = 25 ?c - 11 a t mb = 100 ?c - 7.6 a i dm pulsed drain current t mb = 25 ?c - 44 a p d total power dissipation t mb = 25 ?c - 36 w t j , t stg operating junction and - 55 175 ?c storage temperature d g s 13 tab 2 1 2 3 tab 1 it is not possible to make contact to pin 2 of the sot404 or sot428 package september 1998 1 rev 1.000
philips semiconductors product specification trenchmos ? transistor phb11N06LT, phd11N06LT logic level fet esd limiting value symbol parameter conditions min. max. unit v c electrostatic discharge human body model (100 pf, 1.5 k w )-2kv capacitor voltage, all pins thermal resistances symbol parameter conditions typ. max. unit r th j-mb thermal resistance junction - 4.17 k/w to mounting base r th j-a thermal resistance junction sot78 package, in free air 60 - k/w to ambient sot428 and sot404 package, pcb 50 - k/w mounted, minimum footprint electrical characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit v (br)dss drain-source breakdown v gs = 0 v; i d = 0.25 ma; 55 - - v voltage t j = -55?c 50 - - v v (br)gss gate-source breakdown i g = 1 ma; 10 - - v voltage v gs(to) gate threshold voltage v ds = v gs ; i d = 1 ma 1.0 1.5 2.0 v t j = 175?c 0.5 - - v t j = -55?c - - 2.3 v r ds(on) drain-source on-state v gs = 10 v; i d = 5.5 a - 100 130 m w resistance v gs = 5 v; i d = 5.5 a - 120 150 m w t j = 175?c - 250 315 m w g fs forward transconductance v ds = 25 v; i d = 5.5 a 4 10 - s i gss gate source leakage current v gs = 5 v; v ds = 0 v - 0.02 1 m a t j = 175?c - - 20 m a i dss zero gate voltage drain v ds = 55 v; v gs = 0 v; - 0.05 10 m a current t j = 175?c - - 500 m a q g(tot) total gate charge i d = 11 a; v dd = 44 v; v gs = 5 v - 6.1 - nc q gs gate-source charge - 1.3 - nc q gd gate-drain (miller) charge - 3.2 - nc t d on turn-on delay time v dd = 30 v; i d = 5 a; - 6 16 ns t r turn-on rise time v gs = 5 v; r g = 10 w -2335ns t d off turn-off delay time resistive load - 18 30 ns t f turn-off fall time - 18 30 ns l d internal drain inductance measured from tab to centre of die - 3.5 - nh l s internal source inductance measured from source lead to source - 7.5 - nh bond pad c iss input capacitance v gs = 0 v; v ds = 25 v; f = 1 mhz - 250 330 pf c oss output capacitance - 34 50 pf c rss feedback capacitance - 35 50 pf september 1998 2 rev 1.000
philips semiconductors product specification trenchmos ? transistor phb11N06LT, phd11N06LT logic level fet reverse diode limiting values and characteristics t j = 25?c unless otherwise specified symbol parameter conditions min. typ. max. unit i s continuous source current - - 11 a (body diode) i sm pulsed source current (body - - 44 a diode) v sd diode forward voltage i f = 11 a; v gs = 0 v - 0.95 1.2 v t rr reverse recovery time i f = 11 a; -di f /dt = 100 a/ m s; - 34 - ns q rr reverse recovery charge v gs = 0 v; v r = 30 v - 57 - nc avalanche limiting value symbol parameter conditions min. max. unit w dss drain-source non-repetitive i d 10 a; v dd 25 v; v gs = 5 v; - 10 mj unclamped inductive turn-off r gs = 50 w ; t mb = 25 ?c energy september 1998 3 rev 1.000
philips semiconductors product specification trenchmos ? transistor phb11N06LT, phd11N06LT logic level fet fig.1. normalised power dissipation. pd% = 100 p d /p d 25 ?c = f(t mb ) fig.2. normalised continuous drain current. id% = 100 i d /i d 25 ?c = f(t mb ); conditions: v gs 3 5 v fig.3. safe operating area. t mb = 25 ?c i d & i dm = f(v ds ); i dm single pulse; parameter t p fig.4. transient thermal impedance. z th j-mb = f(t); parameter d = t p /t fig.5. typical output characteristics, t j = 25 ?c . i d = f(v ds ); parameter v gs fig.6. typical on-state resistance, t j = 25 ?c . r ds(on) = f(i d ); parameter v gs 0 20 40 60 80 100 120 140 160 180 tmb / c pd% normalised power derating 120 110 100 90 80 70 60 50 40 30 20 10 0 1us 10us 100us 1ms 10ms 0.1s 1s 10s 0.001 0.01 0.1 1 10 phb11N06LT pulse width, tp (s) transient thermal impedance, zth j-mb (k/w) d = t p t p t t p t d 0 20 40 60 80 100 120 140 160 180 tmb / c id% normalised current derating 120 110 100 90 80 70 60 50 40 30 20 10 0 0246810 0 2 4 6 8 10 phb11N06LT vds, drain-source voltage (volts) id, drain current (amps) vgs = 2.6 v 2.8 v 3 v 3.2 v 3.4 v 3.6 v 5 v 10 v tj = 25 c 1 10 100 0.1 1 10 100 dc phb11N06LT vds, drain-source voltage (volts) id, drain current (amps) rds(on) = vds/id 100 us 1 ms 10 ms 10 us tp = 0246810 0 0.1 0.2 0.3 0.4 0.5 vgs = 5 v phb11N06LT id, drain current (amps) rds(on), drain-source on resistance (ohms) 10 v 2.6v 2.8v 3v 3.2v 3.4v 3.6v tj = 25 c september 1998 4 rev 1.000
philips semiconductors product specification trenchmos ? transistor phb11N06LT, phd11N06LT logic level fet fig.7. typical transfer characteristics. i d = f(v gs ) ; conditions: v ds = 25 v; parameter t j fig.8. typical transconductance, t j = 25 ?c . g fs = f(i d ); conditions: v ds = 25 v fig.9. normalised drain-source on-state resistance. a = r ds(on) /r ds(on)25 ?c = f(t j ); i d = 5.5 a; v gs = 5 v fig.10. gate threshold voltage. v gs(to) = f(t j ); conditions: i d = 1 ma; v ds = v gs fig.11. sub-threshold drain current. i d = f(v gs) ; conditions: t j = 25 ?c; v ds = v gs fig.12. typical capacitances, c iss , c oss , c rss . c = f(v ds ); conditions: v gs = 0 v; f = 1 mhz 012345 0 2 4 6 8 10 phb11N06LT gate-source voltage, vgs (v) drain current, id (a) tj = 25 c 175 c vds > id x rds(on) buk959-60 -100 -50 0 50 100 150 200 0 0.5 1 1.5 2 2.5 tj / c vgs(to) / v max. typ. min. 0246810 0 1 2 3 4 5 6 7 8 phb11N06LT drain current, id (a) transconductance, gfs (s) tj = 25 c tj = 175 c vds > id x rds(on) 0 0.5 1 1.5 2 2.5 3 1e-05 1e-05 1e-04 1e-03 1e-02 1e-01 sub-threshold conduction 2% typ 98% -100 -50 0 50 100 150 200 0.5 1 1.5 2 2.5 buk959-60 tmb / degc rds(on) normlised to 25degc a 0.1 1 10 100 10 100 1000 phb11N06LT drain-source voltage, vds (v) capacitances, ciss, coss, crss (pf) ciss coss crss september 1998 5 rev 1.000
philips semiconductors product specification trenchmos ? transistor phb11N06LT, phd11N06LT logic level fet fig.13. typical turn-on gate-charge characteristics. v gs = f(q g ); parameter v ds fig.14. typical reverse diode current. i f = f(v sds ); conditions: v gs = 0 v; parameter t j fig.15. normalised avalanche energy rating. w dss % = f(t mb ) fig.16. avalanche energy test circuit. 024681012 0 5 10 15 phb11N06LT qg, gate charge (nc) vgs, gate-source voltage (volts) vdd = 44 v id = 11 a tj = 25 c 20 40 60 80 100 120 140 160 180 tmb / c 120 110 100 90 80 70 60 50 40 30 20 10 0 wdss% 0 0.2 0.4 0.6 0.8 1 1.2 1.4 0 5 10 15 20 phb11N06LT vgs = 0v source-drain voltage, vsds (v) source-drain diode current, if (a) tj = 25 c 175 c l t.u.t. vdd rgs r 01 vds -id/100 + - shunt vgs 0 w dss = 0.5 li d 2 bv dss /( bv dss - v dd ) september 1998 6 rev 1.000
philips semiconductors product specification trenchmos ? transistor phb11N06LT, phd11N06LT logic level fet mechanical data dimensions in mm net mass: 1.4 g fig.17. sot404 : centre pin connected to mounting base. mounting instructions dimensions in mm fig.18. sot404 : soldering pattern for surface mounting . notes 1. observe the general handling precautions for electrostatic-discharge sensitive devices (esds) to prevent damage to mos gate oxide. 2. epoxy meets ul94 v0 at 1/8". 11 max 4.5 max 1.4 max 10.3 max 0.5 15.4 2.5 0.85 max (x2) 2.54 (x2) 17.5 11.5 9.0 5.08 3.8 2.0 september 1998 7 rev 1.000
philips semiconductors product specification trenchmos ? transistor phb11N06LT, phd11N06LT logic level fet mechanical data dimensions in mm : net mass: 1.4 g fig.19. sot428 : centre pin connected to mounting base. mounting instructions dimensions in mm fig.20. sot428 : soldering pattern for surface mounting . notes 1. observe the general handling precautions for electrostatic-discharge sensitive devices (esds) to prevent damage to mos gate oxide. 2. epoxy meets ul94 v0 at 1/8". 6.22 max 2.38 max 0.93 max 6.73 max 0.3 10.4 max 0.5 0.8 max (x2) 2.285 (x2) 0.5 seating plane 1.1 0.5 min 5.4 4 min 4.6 1 2 3 tab 7.0 7.0 2.15 2.5 4.57 1.5 september 1998 8 rev 1.000
philips semiconductors product specification trenchmos ? transistor phb11N06LT, phd11N06LT logic level fet definitions data sheet status objective specification this data sheet contains target or goal specifications for product development. preliminary specification this data sheet contains preliminary data; supplementary data may be published later. product specification this data sheet contains final product specifications. limiting values limiting values are given in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of this specification is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the specification. philips electronics n.v. 1998 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. life support applications these products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. september 1998 9 rev 1.000
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